module prbs_generator (
    input wire clk,
    input wire rst,
    input wire enable,
    output reg prbs_bit
);
    reg [7:0] lfsr;

    always @(posedge clk or posedge rst) begin
        if (rst)
            lfsr <= 8'h1; // 非零初值
        else if (enable) begin
            prbs_bit <= lfsr[7];  // 输出最高位作为 PRBS 序列
            lfsr <= {lfsr[6:0], lfsr[7] ^ lfsr[5] ^ lfsr[4] ^ lfsr[3]};
        end
    end

endmodule
